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19-0605; Rev 0; 8/06
Single-/Dual-/Triple-Voltage P Supervisory Circuits with Independent Watchdog Output
General Description
The MAX6730A-MAX6735A single-/dual-/triple-voltage microprocessor (P) supervisors feature a watchdog timer and manual reset capability. The MAX6730A- MAX6735A offer factory-set reset thresholds for monitoring voltages from +0.9V to +5V and an adjustable reset input for monitoring voltages down to +0.63V. The combination of these features significantly improves system reliability and accuracy when compared to separate ICs or discrete components. The active-low reset output asserts and remains asserted for the reset timeout period after all the monitored voltages exceed their respective thresholds. Multiple factoryset reset threshold combinations reduce the number of external components required. The MAX6730A/ MAX6731A monitor a single fixed voltage, the MAX6732A/ MAX6733A monitor two fixed voltages, and the MAX6734A/MAX6735A monitor two fixed voltages and one adjustable voltage. All devices are offered with six minimum reset timeout periods ranging from 1.1ms to 1120ms. The MAX6730A-MAX6735A feature a watchdog timer with an independent watchdog output. The watchdog timer prevents system lockup during code execution errors. A watchdog startup delay of 54s after reset asserts allows system initialization during power-up. The watchdog operates in normal mode with a 1.68s delay after initialization. The MAX6730A/MAX6732A/ MAX6734A provide an active-low, open-drain watchdog output. The MAX6731A/MAX6733A/MAX6735A provide an active-low, push-pull watchdog output. Other features include a manual reset input (MAX6730A/ MAX6731A/MAX6734A/MAX6735A) and push-pull reset output (MAX6731A/MAX6733A/MAX6735A) or opendrain reset output (MAX6730A/MAX6732A/MAX6734A). The MAX6730A-MAX6733A are offered in a tiny 6-pin SOT23 package. The MAX6734A/MAX6735A are offered in an 8-pin, space-saving SOT23 package. All devices are fully specified over the extended -40C to +125C temperature range.
Features
VCC1 (Primary Supply) Reset Threshold Voltages from +1.575V to +4.63V VCC2 (Secondary Supply) Reset Threshold Voltages from +0.79V to +3.08V Adjustable RSTIN Threshold for Monitoring Voltages Down to +0.63V (MAX6734A/MAX6735A Only) Six Reset Timeout Options Watchdog Timer with Independent Watchdog Output 35s (min) Initial Watchdog Startup Period 1.12s (min) Normal Watchdog Timeout Period Manual Reset Input (MAX6730A/MAX6731A/ MAX6734A/MAX6735A) Guaranteed Reset Valid down to VCC1 or VCC2 = +0.8V Push-Pull RESET or Open-Drain RESET Output Immune to Short VCC Transients Low Supply Current: 14A (typ) at +3.6V Small 6-Pin and 8-Pin SOT23 Packages
MAX6730A-MAX6735A
Ordering Information
PART* MAX6730AUT_D_ -T MAX6731AUT_D_ -T MAX6732AUT_ _D_ -T MAX6733AUT_ _D_ -T MAX6734AKA_ _D_ -T MAX6735AKA_ _D_ -T PIN-PACKAGE 6 SOT23-6 6 SOT23-6 6 SOT23-6 6 SOT23-6 8 SOT23-8 8 SOT23-8 PKG CODE U6-1 U6-1 U6-1 U6-1 K8S-3 K8S-3
All devices specified over the -40C to +125C operating temperature range. *Note: Insert the threshold level suffixes for VCC1 and VCC2 (Table 1) after "UT" or "KA." For the MAX6730A/MAX6731A, insert only the VCC1 threshold suffix after the "UT." Insert the reset timeout delay (Table 2) after "D" to complete the part number. For example, the MAX6732AUTLTD3-T provides a VCC1 threshold of +4.625V, a VCC2 threshold of +3.075V, and a 210ms reset timeout period. Sample stock is generally held on standard versions only (see the Standard Versions table). Standard versions have an order increment requirement of 2500 pieces. Nonstandard versions have an order increment requirement of 10,000 pieces. Contact factory for availability. Devices are available in both leaded and lead-free packaging. Specify lead-free by replacing "T" with "+T" when ordering.
Applications
Multivoltage Systems Telecom/Networking Equipment Computers/Servers Portable/Battery-Operated Equipment Industrial Equipment Printer/Fax Set-Top Boxes
Typical Operating Circuit and Pin Configurations appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products
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Single-/Dual-/Triple-Voltage P Supervisory Circuits with Independent Watchdog Output MAX6730A-MAX6735A
ABSOLUTE MAXIMUM RATINGS
VCC1, VCC2, RSTIN, MR, WDI to GND .....................-0.3V to +6V RST, WDO to GND (open drain)...............................-0.3V to +6V RST, WDO to GND (push-pull) .................-0.3V to (VCC1 + 0.3V) Input Current/Output Current (all pins) ...............................20mA Continuous Power Dissipation (TA = +70C) 6-Pin SOT23-6 (derate 8.7mW/C above +70C) ........696mW 8-Pin SOT23-8 (derate 8.9mW/C above +70C) ........714mW Operating Temperature Range .........................-40C to +125C Storage Temperature Range .............................-65C to +150C Junction Temperature ......................................................+150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC1 = VCC2 = +0.8V to +5.5V, TA = -40C to +125C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Supply Voltage SYMBOL VCC1, VCC2 VCC1 < +5.5V, all I/O connections open, outputs not asserted ICC1 Supply Current VCC2 < +3.6V, all I/O connections open, outputs not asserted ICC2 VCC2 < +2.75V, all I/O connections open, outputs not asserted L (falling) M (falling) T (falling) S (falling) VCC1 Reset Threshold VTH1 R (falling) Z (falling) Y (falling) W (falling) V (falling) 4.500 4.250 3.000 2.850 2.550 2.250 2.125 1.620 1.530 4 3 4.625 4.375 3.075 2.925 2.625 2.313 2.188 1.665 1.575 11 9 4.750 4.500 3.150 3.000 2.700 2.375 2.250 1.710 1.620 V VCC1 < +3.6V, all I/O connections open, outputs not asserted CONDITIONS MIN 0.8 15 10 TYP MAX 5.5 39 28 A UNITS V
2
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Single-/Dual-/Triple-Voltage P Supervisory Circuits with Independent Watchdog Output
ELECTRICAL CHARACTERISTICS (continued)
(VCC1 = VCC2 = +0.8V to +5.5V, TA = -40C to +125C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER SYMBOL T (falling) S (falling) R (falling) Z (falling) Y (falling) W (falling) VCC2 Reset Threshold VTH2 V (falling) I (falling) H (falling) G (falling) F (falling) E (falling) D (falling) Reset Threshold Tempco Reset Threshold Hysteresis VHYST Referenced to VTH typical VCC1 = (VTH1 + 100mV) to (VTH1 - 100mV) or VCC2 = (VTH2 + 75mV) to (VTH2 - 75mV) D1 D2 Reset Timeout Period tRP D3 D5 D6 D4 ADJUSTABLE RESET COMPARATOR INPUT (MAX6734A/MAX6735A) RSTIN Input Threshold RSTIN Input Current RSTIN Hysteresis RSTIN to Reset Output Delay tRSTIND VIL VIH 0.7 x VCC1 1 100 tMR 25 200 50 80 VRSTIN to (VRSTIN - 30mV) MANUAL RESET INPUT (MAX6730A/MAX6731A/MAX6734A/MAX6735A) MR Input Threshold MR Minimum Pulse Width MR Glitch Rejection MR to Reset Output Delay MR Pullup Resistance 0.3 x VCC1 V s ns ns k VRSTIN IRSTIN 611 -100 3 22 626.5 642 +100 mV nA mV s 1.1 8.8 140 280 560 1120 CONDITIONS MIN 3.000 2.850 2.550 2.250 2.125 1.620 1.530 1.350 1.275 1.080 1.020 0.810 0.765 TYP 3.075 2.925 2.625 2.313 2.188 1.665 1.575 1.388 1.313 1.110 1.050 0.833 0.788 20 0.5 MAX 3.150 3.000 2.700 2.375 2.250 1.710 1.620 1.425 1.350 1.140 1.080 0.855 0.810 ppm/oC % V UNITS
MAX6730A-MAX6735A
VCC_ to RST Output Delay
tRD
45
s
1.65 13.2 210 420 840 1680
2.2 17.6 280 560 1120 2240 ms
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Single-/Dual-/Triple-Voltage P Supervisory Circuits with Independent Watchdog Output MAX6730A-MAX6735A
ELECTRICAL CHARACTERISTICS (continued)
(VCC1 = VCC2 = +0.8V to +5.5V, TA = -40C to +125C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER WATCHDOG INPUT Watchdog Timeout Period WDI Pulse Width WDI Input Voltage WDI Input Current RESET/WATCHDOG OUTPUT VCC1 or VCC2 +0.8V, ISINK = 1A, output asserted VCC1 or VCC2 +1.0V, ISINK = 50A, output asserted RST / WDO Output Low Voltage (Push-Pull or Open Drain) VOL VCC1 or VCC2 +1.2V, ISINK = 100A, output asserted VCC1 or VCC2 +2.7V, ISINK = 1.2mA, output asserted VCC1 or VCC2 +4.5V, ISINK = 3.2mA, output asserted VCC1 +1.8V, ISOURCE = 200A, output not asserted RST / WDO Output High Voltage (Push-Pull Only) VOH VCC1 +2.7V, ISOURCE = 500A, output not asserted VCC1 +4.5V, ISOURCE = 800A, output not asserted RST / WDO Output Open-Drain Leakage Current Output not asserted 0.8 x VCC1 0.8 x VCC1 0.8 x VCC1 0.5 A V 0.3 0.3 0.3 0.3 0.4 V tWD-L tWD-S tWDI VIL VIH IWDI WDI = 0V or VCC1 0.7 x VCC1 -1 +1 First watchdog period after reset timeout period Normal mode (Note 2) 35 1.12 50 0.3 x VCC1 54 1.68 72 2.24 ns V A s SYMBOL CONDITIONS MIN TYP MAX UNITS
Note 1: Devices tested at TA = +25C. Overtemperature limits are guaranteed by design and not production tested. Note 2: Parameter guaranteed by design.
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Single-/Dual-/Triple-Voltage P Supervisory Circuits with Independent Watchdog Output MAX6730A-MAX6735A
Typical Operating Characteristics
(VCC1 = +5V, VCC2 = +3.3V, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE (VCC1 = +5V, VCC2 = +3.3V)
MAX6730A-35A toc01
SUPPLY CURRENT vs. TEMPERATURE (VCC1 = +3.3V, VCC2 = +2.5V)
MAX6730A-35A toc02
SUPPLY CURRENT vs. TEMPERATURE (VCC1 = +2.5V, VCC2 = +1.8V)
18 16 SUPPLY CURRENT (A) 14 12 10 8 6 4 2 0 ICC2 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) ICC1 TOTAL
MAX6730A-35A toc03 MAX6730A-35A toc05
20 18 16 SUPPLY CURRENT (A) 14 12 10 8 6 4 2 0 ICC2 ICC1 TOTAL
20 18 16 SUPPLY CURRENT (A) 14 12 10 8 6 4 2 0 ICC2 ICC1 TOTAL
20
-40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
-40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
SUPPLY CURRENT vs. TEMPERATURE (VCC1 = +1.8V, VCC2 = +1.2V)
NORMALIZED THRESHOLD VOLTAGE 18 16 SUPPLY CURRENT (A) 14 12 10 8 6 4 2 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) ICC2 TOTAL ICC1
MAX6730A-35A toc04
NORMALIZED THRESHOLD VOLTAGE vs. TEMPERATURE
1.008 1.007 1.006 1.005 1.004 1.003 1.002 1.001 1.000 0.999 0.998 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
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Single-/Dual-/Triple-Voltage P Supervisory Circuits with Independent Watchdog Output MAX6730A-MAX6735A
Typical Operating Characteristics (continued)
(VCC1 = +5V, VCC2 = +3.3V, TA = +25C, unless otherwise noted.)
NORMALIZED TIMEOUT PERIOD vs. TEMPERATURE
MAX6730A-35A toc06
MAXIMUM VCC_ TRANSIENT DURATION vs. RESET THRESHOLD OVERDRIVE
MAXIMUM VCC_ TRANSIENT DURATION (s)
MAX6730A-35A toc07
MR TO RESET OUTPUT DELAY
MAX6730A-35A toc08
1.020 1.016 NORMALIZED TIMEOUT PERIOD 1.012 1.008 1.004 1.000 0.996 0.992 0.988 0.984 0.980
10,000
1000
RST ASSERTS ABOVE THIS LINE
MR 2V/div
100 RST 2V/div 10
-40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
1
10
100
1000
40ns/div
RESET THRESHOLD OVERDRIVE (mV)
VCC_ TO RESET OUTPUT DELAY vs. TEMPERATURE
19 18 17 16 15 14 13 12 11 10 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) 12 75mV OVERDRIVE
MAX6730A-35A toc09
RSTIN TO RESET OUTPUT DELAY vs. TEMPERATURE
MAX6730A-35A toc10
20 VCC_ TO RESET OUTPUT DELAY (s)
24 RSTIN RESET OUTPUT DELAY (s) 22 20 18 16 14
-40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
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Single-/Dual-/Triple-Voltage P Supervisory Circuits with Independent Watchdog Output
Pin Description
PIN MAX6730A MAX6731A MAX6732A MAX6733A MAX6734A MAX6735A NAME FUNCTION Active-Low Reset Output. The MAX6730A/MAX6732A/MAX6734A provide an open-drain output. The MAX6731A/MAX6733A/MAX6735A provide a push-pull output. RST asserts low when any of the following conditions occur: VCC1 or VCC2 drops below its preset threshold, RSTIN drops below its reset threshold, or MR is driven low. Open-drain versions require an external pullup resistor. Ground Active-Low Watchdog Output. The MAX6730A/MAX6732A/MAX6734A provide an open-drain WDO output. The MAX6731A/MAX6733A/MAX6735A provide a push-pull WDO output. WDO asserts low when no low-to-high or high-to-low transition occurs on WDI within the watchdog timeout period (tWD) or if an undervoltage-lockout condition exists for VCC1, VCC2, or RSTIN. WDO deasserts without a timeout period when VCC1, VCC2, and RSTIN exceed their reset thresholds, or when the manual reset input is deasserted. Open-drain versions require an external pullup resistor. Active-Low Manual Reset Input. Drive MR low to force a reset. RST remains asserted as long as MR is low and for the reset timeout period after MR releases high. MR has a 50k pullup resistor to VCC1; leave MR open or connect to VCC1 if unused. Watchdog Input. If WDI remains high or low for longer than the watchdog timeout period, the internal watchdog timer expires and the watchdog output asserts low. The internal watchdog timer clears whenever RST asserts or a rising or falling edge on WDI is detected. The watchdog has an initial watchdog timeout period (35s min) after each reset event and a short timeout period (1.12s min) after the first valid WDI transition. Floating WDI does not disable the watchdog timer function. Primary Supply-Voltage Input. VCC1 provides power to the device when it is greater than VCC2. VCC1 is the input to the primary reset threshold monitor. Secondary Supply-Voltage Input. VCC2 provides power to the device when it is greater than VCC1. VCC2 is the input to the secondary reset threshold monitor. Undervoltage Reset Comparator Input. RSTIN provides a high-impedance comparator input for the adjustable reset monitor. RST asserts low if the voltage at RSTIN drops below the 626mV internal reference voltage. Connect a resistive voltage-divider to RSTIN to monitor voltages higher than 626mV. Connect RSTIN to VCC1 or VCC2 if unused.
MAX6730A-MAX6735A
1
1
1
RST
2
2
2
GND
3
3
4
WDO
4
--
5
MR
5
5
3
WDI
6 --
6 4
8 6
VCC1 VCC2
--
--
7
RSTIN
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Single-/Dual-/Triple-Voltage P Supervisory Circuits with Independent Watchdog Output MAX6730A-MAX6735A
Table 1. Reset Voltage Threshold Suffix Guide**
PART NUMBER SUFFIX LT MS MR TZ SY RY TW SV RV TI SH RH TG SF RF TE SD RD ZW YV ZI YH ZG YF ZE YD WI VH WG VF WE VD VCC1 NOMINAL VOLTAGE THRESHOLD(V) 4.625 4.375 4.375 3.075 2.925 2.625 3.075 2.925 2.625 3.075 2.925 2.625 3.075 2.925 2.625 3.075 2.925 2.625 2.313 2.188 2.313 2.188 2.313 2.188 2.313 2.188 1.665 1.575 1.665 1.575 1.665 1.575 VCC2 NOMINAL VOLTAGE THRESHOLD (V) 3.075 2.925 2.625 2.313 2.188 2.188 1.665 1.575 1.575 1.388 1.313 1.313 1.110 1.050 1.050 0.833 0.788 0.788 1.665 1.575 1.388 1.313 1.110 1.050 0.833 0.788 1.388 1.313 1.110 1.050 0.833 0.788
Table 2. Reset Timeout Period Suffix Guide
TIMEOUT PERIOD SUFFIX D1 D2 D3 D5 D6 D4 ACTIVE TIMEOUT PERIOD MIN (ms) 1.1 8.8 140 280 560 1120 MAX (ms) 2.2 17.6 280 560 1120 2240
Detailed Description
Supply Voltages
The MAX6730A-MAX6735A microprocessor (P) supervisors maintain system integrity by alerting the P to fault conditions. The MAX6730A-MAX6735A monitor one to three supply voltages in P-based systems and assert an active-low reset output when any monitored supply voltage drops below its preset threshold. The output state remains valid for VCC1 or VCC2 greater than +0.8V.
Threshold Levels
The two-letter code in the Reset Voltage Threshold Suffix Guide (Table 1) indicates the threshold level combinations for VCC1 and VCC2.
Reset Output
The MAX6730A-MAX6735A feature an active-low reset output (RST). RST asserts when the voltage at either VCC1 or VCC2 falls below the voltage threshold level, VRSTIN drops below its threshold, or MR is driven low (Figure 1). RST remains low for the reset timeout period (Table 2) after VCC1, VCC2, and RSTIN increase above their respective thresholds and after MR releases high. Whenever VCC1, VCC2, or RSTIN go below the reset threshold before the end of the reset timeout period, the internal timer restarts. The MAX6730A/MAX6732A/ MAX6734A provide an open-drain RST output, and the MAX6731A/MAX6733A/MAX6735A provide a push-pull RST output.
**Standard versions are shown in bold and are available in a D3 timeout option only. Standard versions require 2500-piece order increments and are typically held in sample stock. There is a 10,000-piece order increment on nonstandard versions. Other threshold voltages may be available; contact factory for availability.
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Single-/Dual-/Triple-Voltage P Supervisory Circuits with Independent Watchdog Output MAX6730A-MAX6735A
VCC1, VCC2 RSTIN VCC (MIN) VTH
RST
tRP
tRP
WDO
MR
Figure 1. RST, WDO, and MR Timing Diagram
Manual Reset Input
Many P-based products require manual reset capability, allowing the operator, a test technician, or external logic circuitry to initiate a reset. A logic-low on MR asserts the reset output, clears the watchdog timer, and deasserts the watchdog output. Reset remains asserted while MR is low and for the reset timeout period (tRP) after MR returns high. An internal 50k pullup resistor allows MR to be left open if unused. Drive MR with CMOS-logic levels or with open-drain/collector outputs. Connect a normally open momentary switch from MR to GND to create a manual reset function; external debounce circuitry is not required. Connect a 0.1F capacitor from MR to GND to provide additional noise immunity when driving MR over long cables or if the device is used in a noisy environment.
VEXT_TH
R1
MAX6734A MAX6735A
RSTIN
R2 GND
Adjustable Input Voltage (RSTIN)
The MAX6734A/MAX6735A provide an additional highimpedance comparator input with a 626mV threshold to monitor a third supply voltage. To monitor a voltage higher than 626mV, connect a resistive divider to the circuit as shown in Figure 2 to establish an externally controlled threshold voltage, VEXT_TH. VEXT_TH = 626mV x (R1 + R2) R2
Figure 2. Monitoring a Third Voltage
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Single-/Dual-/Triple-Voltage P Supervisory Circuits with Independent Watchdog Output MAX6730A-MAX6735A
The RSTIN comparator derives power from VCC1, and the input voltage must remain less than or equal to VCC1. Low leakage current at RSTIN allows the use of large-valued resistors, resulting in reduced power consumption of the system. The usual watchdog timeout period (1.12s min) begins after the initial watchdog timeout period (tWD-L) expires or after the first transition on WDI (Figure 3). During normal operating mode, the supervisor asserts the WDO output if the P does not update the WDI with a valid transition (high to low or low to high) within the standard timeout period (tWD-S) (1.12s min). Connect MR to WDO to force a system reset in the event that no rising or falling edge is detected at WDI within the watchdog timeout period. WDO asserts low when no edge is detected by WDI, the RST output asserts low, the watchdog counter immediately clears, and WDO returns high. The watchdog counter restarts, using the long watchdog period, when the reset timeout period ends (Figure 4).
Watchdog
The watchdog feature monitors P activity through the watchdog input (WDI). A rising or falling edge on WDI within the watchdog timeout period (t WD) indicates normal P operation. WDO asserts low if WDI remains high or low for longer than the watchdog timeout period. Floating WDI does not disable the watchdog timer. The MAX6730A-MAX6735A include a dual-mode watchdog timer to monitor P activity. The flexible timeout architecture provides a long-period initial watchdog mode, allowing complicated systems to complete lengthy boots, and a short-period normal watchdog mode, allowing the supervisor to provide quick alerts when processor activity fails. After each reset event (VCC power-up, brownout, or manual reset), there is a long initial watchdog period of 35s (min). The long watchdog period mode provides an extended time for the system to power up and fully initialize all P and system components before assuming responsibility for routine watchdog updates.
Ensuring a Valid Reset Output Down to VCC = 0V
The MAX6730A-MAX6735A guarantee proper operation down to VCC = +0.8V. In applications that require valid reset levels down to VCC = 0V, use a 100k pulldown resistor from RST to GND. The resistor value used is not critical, but it must be large enough not to load the reset output when V CC is above the reset threshold. For most applications, 100k is adequate. Note that this configuration does not work for the opendrain outputs of MAX6730A/MAX6732A/MAX6734A.
VCC1, VCC2 RSTIN
VCC (MIN)
VTH
RST
tRP
WDO
WDI

>tWD-S

tWD-S
Figure 3. Watchdog Input/Output Timing Diagram (MR and WDO Not Connected) 10 ______________________________________________________________________________________
Single-/Dual-/Triple-Voltage P Supervisory Circuits with Independent Watchdog Output MAX6730A-MAX6735A
VCC1, VCC2 RSTIN VCC (MIN) VTH
RST
tRP
tRP
WDO
WDI

>tWD-S

MR
tMR
Figure 4. Watchdog Input/Output Timing Diagram (MR and WDO Connected)
Applications Information
Interfacing to Ps with Bidirectional Reset Pins
Microprocessors with bidirectional reset pins can interface directly with the open-drain RST output options. However, conditions might occur in which the push-pull output versions experience logic contention with the bidirectional reset pin of the P. Connect a 10k resistor between RST and the P's reset I/O port to prevent logic contention (Figure 5).
VCC2 VCC1 RESET TO OTHER SYSTEM COMPONENTS 10k RESET P
VCC1
MAX6731A MAX6733A RST MAX6735A
VCC2
Falling VCC Transients
The MAX6730A-MAX6735A P supervisors are relatively immune to short-duration falling VCC _ transients (glitches). Small glitches on VCC_ are ignored by the MAX6730A-MAX6735A, preventing undesirable reset pulses to the P. The Typical Operating Characteristics show Maximum V CC_ Transient Duration vs. Reset
GND GND
Figure 5. Interfacing to Ps with Bidirectional Reset I/O 11
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Single-/Dual-/Triple-Voltage P Supervisory Circuits with Independent Watchdog Output MAX6730A-MAX6735A
Threshold Overdrive graph, for which reset pulses are not generated. The graph was produced using falling VCC_ pulses, starting above VTH and ending below the reset threshold by the magnitude indicated (reset threshold overdrive). The graph shows the maximum pulse width that a falling VCC transient typically might have without causing a reset pulse to be issued. As the amplitude of the transient increases (i.e., goes further below the reset threshold), the maximum allowable pulse width decreases. A 0.1F bypass capacitor mounted close to VCC_ provides additional transient immunity.
Functional Diagram
VCC1 MR VCC1
MAX6730A- MAX6735A
MR PULLUP
VCC1 VCC2 VREF RESET TIMEOUT PERIOD
VCC1
VCC2 RST
Watchdog Software Considerations
Setting and resetting the watchdog input at different points in the program rather than "pulsing" the watchdog input high-low-high or low-high-low helps the watchdog timer closely monitor software execution. This technique avoids a "stuck" loop, in which the watchdog timer continues to be reset within the loop, preventing the watchdog from timing out. Figure 6 shows an example flow diagram in which the I/O driving the watchdog input is set high at the beginning of the program, set low at the beginning of every subroutine or loop, and then set high again when the program returns to the beginning. If the program "hangs" in any subroutine, the I/O continually asserts low (or high), and the watchdog timer expires, issuing a reset or interrupt.
RESET OUTPUT DRIVER
VCC1 WDO
RSTIN
WATCHDOG TIMER
WDI
VCC1 REF VREF / 2 GND
START
SET WDI HIGH PROGRAM CODE
SUBROUTINE OR PROGRAM LOOP SET WDI LOW SUBROUTINE COMPLETED RETURN HANG IN SUBROUTINE
Figure 6. Watchdog Flow Diagram
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Single-/Dual-/Triple-Voltage P Supervisory Circuits with Independent Watchdog Output
Standard Versions
PART MAX6730AUTLD3-T MAX6730AUTSD3-T MAX6730AUTRD3-T MAX6730AUTZD3-T MAX6730AUTVD3-T MAX6731AUTLD3-T MAX6731AUTTD3-T MAX6731AUTSD3-T MAX6731AUTRD3-T MAX6731AUTZD3-T MAX6731AUTVD3-T MAX6732AUTLTD3-T MAX6732AUTSYD3-T MAX6732AUTSVD3-T MAX6732AUTRVD3-T MAX6732AUTSHD3-T MAX6732AUTTGD3-T MAX6732AUTSDD3-T MAX6732AUTZWD3-T MAX6732AUTYHD3-T MAX6732AUTZGD3-T MAX6732AUTYDD3-T MAX6732AUTVHD3-T MAX6732AUTWGD3-T MAX6732AUTVDD3-T MAX6733AUTLTD3-T MAX6733AUTSYD3-T MAX6733AUTSVD3-T MAX6733AUTRVD3-T MAX6733AUTSHD3-T MAX6733AUTTGD3-T MAX6733AUTSDD3-T MAX6733AUTZWD3-T MAX6733AUTYHD3-T TOP MARK +ACIX +ACJA +ACIY +ACJF +ACJC +ACJG +ACJJ +ACJI +ACJH +ACJL +ACJK +ACHU +ACHZ +ACHY +ACHV +ACHX +ACIA +ACHW +ACIH +ACIF +ACIG +ACIE +ACIC +ACID +ACIB +ACII +ACIN +ACIM +ACIJ +ACIL +ACIO +ACIK +ACIW +ACIU PART MAX6733AUTZGD3-T MAX6733AUTYDD3-T MAX6733AUTVHD3-T MAX6733AUTWGD3-T MAX6733AUTVDD3-T MAX6734AKALTD3-T MAX6734AKASYD3-T MAX6734AKASVD3-T MAX6734AKARVD3-T MAX6734AKASHD3-T MAX6734AKATGD3-T MAX6734AKASDD3-T MAX6734AKAZWD3-T MAX6734AKAYHD3-T MAX6734AKAZGD3-T MAX6734AKAYDD3-T MAX6734AKAVHD3-T MAX6734AKAWGD3-T MAX6734AKAVDD3-T MAX6735AKALTD3-T MAX6735AKASYD3-T MAX6735AKASVD3-T MAX6735AKARVD3-T MAX6735AKASHD3-T MAX6735AKATGD3-T MAX6735AKASDD3-T MAX6735AKAZWD3-T MAX6735AKAZID3-T MAX6735AKAYHD3-T MAX6735AKAZGD3-T MAX6735AKAYDD3-T MAX6735AKAVHD3-T MAX6735AKAWGD3-T MAX6735AKAVDD3-T TOP MARK +ACIV +ACIT +ACIR +ACIS +ACIQ +AENS +AENZ +AENY +AENU +AENX +AEOA +AENV +AEOI +AEOG +AEOH +AEOF +AEOD +AEOE +AEOC +AEOJ +AEOO +AEON +AEOK +AEOM +AEOP +AEOL +AEOX +AEOW +AEOU +AEOV +AEOT +AEOR +AEOS +AEOQ
MAX6730A-MAX6735A
Note: Sample stock is generally held on standard versions only. Standard versions have an order increment requirement of 2500 pieces. Nonstandard versions have an order increment requirement of 10,000 pieces. Contact factory for availability of nonstandard versions.
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13
Single-/Dual-/Triple-Voltage P Supervisory Circuits with Independent Watchdog Output MAX6730A-MAX6735A
Pin Configurations
TOP VIEW
RST 1 6 VCC1 RST 1 6 VCC1 RST GND 5 WDI WDI 1 2 3 8 7 VCC1 RSTIN VCC2 MR
GND 2
MAX6730A MAX6731A
5
WDI
GND 2
MAX6732A MAX6733A
MAX6734A MAX6735A
6 5
WDO 3
4
MR
WDO 3
4
VCC2
WDO 4
SOT23-6
SOT23-6
SOT23-8
Typical Operating Circuit
+1.8V +0.9V VCORE +3.3V
___________________Chip Information
TRANSISTOR COUNT: 1073 PROCESS: BiCMOS
VCC2 RSTIN
VCC1 RST
VCC (I/O) RESET
VDD (MEMORY)
MAX6734A WDI MAX6735A
PUSHBUTTON SWITCH WDO MR GND
I/O
P
NMI
GND
Selector Guide
PART NUMBER MAX6730A MAX6731A MAX6732A MAX6733A MAX6734A MAX6735A VOLTAGE MONITORS 1 1 2 2 3 3 RST OUTPUT Open Drain Push-Pull Open Drain Push-Pull Open Drain Push-Pull MANUAL RESET -- -- WATCHDOG INPUT WATCHDOG OUTPUT Open Drain Push-Pull Open Drain Push-Pull Open Drain Push-Pull
14
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Single-/Dual-/Triple-Voltage P Supervisory Circuits with Independent Watchdog Output MAX6730A-MAX6735A
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
6LSOT.EPS
PACKAGE OUTLINE, SOT 6L BODY
21-0058
G
1 1
______________________________________________________________________________________
15
Single-/Dual-/Triple-Voltage P Supervisory Circuits with Independent Watchdog Output MAX6730A-MAX6735A
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
SOT23, 8L .EPS
REV.
SEE DETAIL "A" b
C L
e
SYMBOL A A1 A2 b C D E E1 L L2 e e1
MIN 0.90 0.00 0.90 0.22 0.08 2.80 2.60 1.50 0.30
MAX 1.45 0.15 1.30 0.38 0.22 3.00 3.00 1.75 0.60 0.25 BSC. 0.65 BSC. 1.95 REF.
C L
E
C L
E1
PIN 1 I.D. DOT (SEE NOTE 6) e1 D C
C L
0
0
8
L2 A A2 A1
SEATING PLANE C
GAUGE PLANE
L
0
NOTE:
1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. FOOT LENGTH MEASURED FROM LEAD TIP TO UPPER RADIUS OF HEEL OF THE LEAD PARALLEL TO SEATING PLANE C. 3. PACKAGE OUTLINE EXCLUSIVE OF MOLD FLASH & METAL BURR. 4. PACKAGE OUTLINE INCLUSIVE OF SOLDER PLATING. 5. COPLANARITY 4 MILS. MAX. 6. PIN 1 I.D. DOT IS 0.3 MM O MIN. LOCATED ABOVE PIN 1.
PROPRIETARY INFORMATION
DETAIL "A"
7. SOLDER THICKNESS MEASURED AT FLAT SECTION OF LEAD BETWEEN 0.08mm AND 0.15mm FROM LEAD TIP. 8. MEETS JEDEC MO178 VARIATION BA.
TITLE:
PACKAGE OUTLINE, SOT-23, 8L BODY
APPROVAL DOCUMENT CONTROL NO.
21-0078
1 1
E
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2006 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
Heaney

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